#################################################################################
# File: xdc file about board MK7160FA
# Author: Abu liu
# Data: 2020.9.21
# Note: Based on xdc file provided by MSXBO
#################################################################################

# adv7611 configuration iic
set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS33}  [get_ports adv_iic_scl]
set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS33}  [get_ports adv_iic_sda]

# adv7611 misc signals
set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS33}  [get_ports adv_clk]
set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS33}  [get_ports adv_vs]
set_property -dict {PACKAGE_PIN AE22 IOSTANDARD LVCMOS33}  [get_ports adv_de]
set_property -dict {PACKAGE_PIN A13  IOSTANDARD LVCMOS33}  [get_ports adv_rst]

# adv7611 data signals
set_property PACKAGE_PIN W20  [get_ports {adv_data[0]}]
set_property PACKAGE_PIN AC22 [get_ports {adv_data[1]}]
set_property PACKAGE_PIN AB22 [get_ports {adv_data[2]}]
set_property PACKAGE_PIN AF25 [get_ports {adv_data[3]}]
set_property PACKAGE_PIN AF24 [get_ports {adv_data[4]}]
set_property PACKAGE_PIN AF23 [get_ports {adv_data[5]}]
set_property PACKAGE_PIN AE23 [get_ports {adv_data[6]}]
set_property PACKAGE_PIN AE21 [get_ports {adv_data[7]}]

set_property PACKAGE_PIN Y21  [get_ports {adv_data[8]}]
set_property PACKAGE_PIN AB24 [get_ports {adv_data[9]}]
set_property PACKAGE_PIN AB21 [get_ports {adv_data[10]}]
set_property PACKAGE_PIN AC21 [get_ports {adv_data[11]}]
set_property PACKAGE_PIN W23  [get_ports {adv_data[12]}]
set_property PACKAGE_PIN W24  [get_ports {adv_data[13]}]
set_property PACKAGE_PIN AD25 [get_ports {adv_data[14]}]
set_property PACKAGE_PIN AE25 [get_ports {adv_data[15]}]

set_property PACKAGE_PIN AC23 [get_ports {adv_data[16]}]
set_property PACKAGE_PIN AC24 [get_ports {adv_data[17]}]
set_property PACKAGE_PIN AD26 [get_ports {adv_data[18]}]
set_property PACKAGE_PIN AE26 [get_ports {adv_data[19]}]
set_property PACKAGE_PIN AA25 [get_ports {adv_data[20]}]
set_property PACKAGE_PIN AB25 [get_ports {adv_data[21]}]
set_property PACKAGE_PIN AB26 [get_ports {adv_data[22]}]
set_property PACKAGE_PIN AC26 [get_ports {adv_data[23]}]

set_property IOSTANDARD LVCMOS33 [get_ports {adv_data[*]}]

create_clock -period 6.734 -name adv_clk -waveform {0.000 3.367} [get_ports adv_clk]

# PCIE
set_property -dict {PACKAGE_PIN A12 IOSTANDARD LVCMOS33}  [get_ports pcie_resetn]

# PCI Express reference clock 100MHz
set_property PACKAGE_PIN K6   [get_ports {pcie_sys_clk_clk_p}]
create_clock -period 10.000 -name pcie_sys_clk [get_ports {pcie_sys_clk_clk_p}]

# MGT locations
set_property PACKAGE_PIN R4 [get_ports {pcie_mgt_rxp[3]}]
set_property PACKAGE_PIN N4 [get_ports {pcie_mgt_rxp[2]}]
set_property PACKAGE_PIN L4 [get_ports {pcie_mgt_rxp[1]}]
set_property PACKAGE_PIN J4 [get_ports {pcie_mgt_rxp[0]}]

set_property PACKAGE_PIN P2 [get_ports {pcie_mgt_txp[3]}]
set_property PACKAGE_PIN M2 [get_ports {pcie_mgt_txp[2]}]
set_property PACKAGE_PIN K2 [get_ports {pcie_mgt_txp[1]}]
set_property PACKAGE_PIN H2 [get_ports {pcie_mgt_txp[0]}]

#DCI
set_property DCI_CASCADE {32 34} [get_iobanks 33]
#bit compress spix4 speed up
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE Yes [current_design]